1. Field of the Invention
The invention relates to a method for reading a memory cell, and more particularly to a method for stably reading a memory cell.
2. Description of the Related Art
Demand for semiconductor memory devices (or memory devices) have increased because of their advantages. Of the different types of memory devices, magnetic random access memory (MRAM), resistive random-access memory (RRAM), and phase change memory (PCM) have random accessibility, higher integration and greater capacity storage when compared to other memory devices.
A phase change memory (PCM) or phase-change random access memory (PRAM) is based on a volume of chalcogenide alloy, which, after being heated and cooled, adopts one of two stable, but programmable, phases: a crystalline state or an amorphous state. The key to the phase-change memory is the chalcogenide material. The device historically includes an alloy of germanium (Ge), antimony (Sb) and tellurium (Te), which is referred to commonly as a GST alloy. The material is particularly useful for incorporation in a memory device because of its ability to switch rapidly, when heated and cooled, between the stable amorphous and crystalline phases.
For materials used in PCMs or PRAMs, resistance of a first phase, i.e., a crystalline phase, is relatively low, and the resistance of a second phase, i.e., the amorphous phase, is relatively high. The state of the cell is programmed to a logical one (1) or zero (0), depending upon the phase of the programmable volume, and measured resistance. The crystalline state is commonly referred to as the “set”, or “0”, state and the amorphous state is commonly referred to as the “reset”, or “1”, state.
Recently, a technique for storing more than 2-bit data in one memory cell has been disclosed. This type of memory cell is generally referred to as a multi-level cell (MLC). A multi-level phase change memory device is a low-cost non-volatile memory device having high memory capacity. In a multi-level phase change memory device, there are intermediate states between a reset state and a set state.
However, for multi-level phase change memory devices including chalcogenide containing amorphous material, the resistance of the chalcogenide containing amorphous material drifts upward over time (e.g., following the power law (t/t0)r, with r˜0.1), as much as a factor of 4, within 106 seconds, as shown in FIG. 1 and disclosed in Karpov et al., J. Appl. Phys. 102, 124503 (2007). This poses a problem for operation of the multi-level phase change memory device, where two adjacent resistance states may need to be separated by a factor of 1.5-2.
FIG. 2 is a graph illustrating time against resistance of a multi-level phase change memory cell in which data are programmed into a state 11, a state 10, a state 01 and a state 00. The freshly programmed resistance state 11 of a resistance R0 at time t1 would be confused with the resistance state 10 that was programmed at time t2. For this reason, the operation of multilevel phase change memory as high bit density technology is prohibited unless a different method of operation avoiding the drift consequence is used. It should also be noted that other non-volatile resistance-based memories based on materials such as TiO2, are also vulnerable to resistance drift (e.g., B. J. Choi et al., J. Appl. Phys. 98, 033715 (2005)).
U.S. Pat. Pub. 2009/0016100 discloses a phase change memory device and a reading method thereof. The method programs a reference array along with a read/write block. However, the read/write operation and required structure result in excess time and power consumption as well as extra chip area, leading to higher manufacturing cost.